Microsoft details Maia 300 chiplet inference architecture ahead of 2027 deployment

Microsoft has detailed Maia 300, its third-generation custom inference system, with a multi-chiplet architecture that separates compute, memory-controller and I/O functions. Compute chiplets use TSMC's N2P process; the system is designed for long-context reasoning and multi-step agent workloads where moving data can matter as much as raw compute. Company specifications include eight HBM4 stacks with 18 TB/s peak bandwidth within a 950 W chip power envelope, and 96 accelerators per 167 kW rack. Microsoft expects 40% more tokens per megawatt than leading GPU-based systems and up to 7x Maia 200 rack throughput. These are company projections, not independently reproduced comparisons; workload and system configuration affect the result. Maia 300 production deployments begin in 2027, not now. Maia 200 is already serving production workloads, including Copilot. The October 12 announcement combines a new architecture disclosure with a future multi-gigawatt rollout plan. The supplied image is an official chip promotional visual, not evidence that Maia 300 is shipping.

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