IIT Delhi demonstrates programmable micro-GPU on FPGA for embedded displays

IIT Delhi researchers have demonstrated programmable graphics rendering with a custom floating-point micro-GPU engine written in register-transfer language and implemented on a Spartan-7 FPGA. The work targets embedded displays and affordable visualisation systems, rather than an announced mass-produced GPU or a high-end AI training accelerator. M.Tech students Nammi Akash and M. Ravi Teja led the project under Prof. Jayadeva and Prof. Kaushik Saha in IIT Delhi's Electrical Engineering Department. The institute lists possible applications including industrial control displays, low-cost human-machine interfaces, e-rickshaw dashboards, navigation terminals for small fishing boats and educational e-book readers. These are intended uses, not reported commercial deployments. The team is exploring an 8-16-core vector-style architecture, an optimised compiler and graphics toolchain, and eventual proof-of-concept implementation at a 65nm ASIC process node. Those steps remain a roadmap. The researchers plan to seek funding for ASIC development, system integration and commercialisation; the release does not announce funding secured or fabricated ASIC silicon. IIT Delhi's 'first indigenous micro-GPU' claim is attributed to the researchers' knowledge, not independently established here.

DTT summary based on IIT Delhi's report. The full article is on the publisher's site.